NeuroStack

Pattern Learning and Recognition Accelerator for Data Analytics

Description

Accelerate your video analytics and deep learning with to a highly scalable and trainable neural network with a deterministic latency.

NeuroStack has unique architecture featuring four NeuroMem CM1K chips and a Field Programmable Gate Array to perform high speed pattern learning and recognition. The default FPGA configuration cascade the CM1K in a single NN totalling 4096 neurons, but they can be arranged otherwise. Also, the NN capacity can be expanded by stacking NeuroStack boards. This means that you can start training on one NeuroStack, and if/when you find out that you need more neurons, you can save the knowledge built by the neurons, stack a 2nd NeuroStack and simply reload the knowledge before resuming training and without changing anything to your software API or UI.

Specifications
  • Four CM1K chips (1024 neurons per chip. Configured as single network of 4096 neurons in default FPGA configuration)
  • Lattice XP2 Field Programmable Gate Araay with 40,000 logic elements
  • Four banks of I/O lines
  • Two banks of 2 Mbytes (2M x16bits) MRAM, 35 ns access time
  • FTDI USB2 chip
  • NeuroStack Hardware Manual
  • NeuroStack Firmware Manual (factory default)
  • Stackable via pogo pins connectors
Block Diagram