NeuroStack

Pattern Learning and Recognition Accelerator Inquire
Description

Accelerate your video analytics and deep learning with to a highly scalable and trainable neural network with a deterministic latency.

NeuroStack has unique architecture featuring four NeuroMem CM1K chips and a Field Programmable Gate Array to perform high speed pattern learning and recognition. The default FPGA configuration cascade the CM1K in a single NN totalling 4096 neurons, but they can be arranged otherwise.

Specifications
  • Four CM1K chips (1024 neurons per chip. Configured as single network of 4096 neurons in default FPGA configuration)
  • Lattice XP2 Field Programmable Gate Araay with 40,000 logic elements
  • Four banks of I/O lines
  • Two banks of 2 Mbytes (2M x16bits) MRAM, 35 ns access time
  • FTDI USB2 chip
  • NeuroStack Hardware Manual
  • NeuroStack Firmware Manual (factory default)
  • Stackable via pogo pins connectors

Tools (included)

CogniPat SDK (Windows; choice of the standard C/C++, or MatLab, or LabVIEW SDK)

NeuroMem Knowledge Builder (Windows)

FPGA Firmware (Lattice Diamond project including the Verilog source code of the NeuroStack default firmware)