Learn on the chip. Stimuli can derive from text, bio-signals, audio files, images and videos, etc.

Real Time

Recognize patterns in micro-seconds regardless of the number of models stored in the neurons.

Energy Efficient

100,000 recognitions per second at 27Mhz. Less than 0.5 milliWatts per 1000 neurons.

Available NOW

Available on  ASICs, SOCs, and FPGAs and can be evaluated on a variety of platforms

Hardware neurons inspired by biology

  • All interconnected and working in parallel, recognizing or learning one pattern in a constant number of nsec and this regardless of the number of neurons committed in the chip
  • Behave collectively as (1) a K-Nearest Neighbor or (2) a Radial Basis Function (more specifically a Restricted Coulomb Energy classifier). They can cope with ill-defined and fuzzy data, high variability of context and novelty detection.
  • Collective built-in model generator which means that learning is done on the chip!
  • Last, but not least, multiple NeuroMem chips can be daisy-chained to scale a network from thousands to millions of neurons with the same speed performance and simplicity of operation as a single chip.

The Flavors of NeuroMem…

CM1K chip

  • 1024 neurons
  • 256 bytes of memory per neuron
  • Cascadable
  • I2C (optional use)
  • Recognition stage (optional use)

Intel Quark SE

  • 128 neurons
  • 128 bytes of memory per neuron
  • Component of an SOC also combining an x86 MCU and a sensor subsystem

NM500 chip

  • 576 neurons
  • 256 bytes of memory per neuron
  • Cascadable
  • Wafer scale package

NeuroMem IP

  • NeuroMem IP for FPGA
  • NeuroMem IP for SOC
  • Custom neuron capacity
  • Custom memory capacity per neuron

Evaluation platforms

  • BrainCard with NM500 (Q4, 2017)
  • FPGA platforms (Lattice, Xillinx, Altera)

More to come…

State of the Art for neuromorphic chips

Of the Illusions of AI“, an objective review from the 80’s til today by Luca Marchese.

In the past decade, the renewed interest for neuromorphic chips has awakened competition from companies such as IBM with its TrueNorth chip, QualComm with the Zeroth chip, and more (see market report). Their periodic mediatic campaigns are getting everyone accustomed to the fact that brain-like chips are coming to the market, but where are these chips? And to whom will they be accessible?

  • 1987: Darpa publishes a Neural Network Study concluding that neural network has matured greatly since the Perceptron of the 50’s, but hardware capabilities are limiting its development.
  • 1993: The ZISC chip was invented by Guy Paillet, our CEO, and jointly developed with IBM-France, at the same time as the joint venture between Nestor and Intel was working on the NI1000 chip. The ZISC had 36 neurons and later 78 neurons.
  • 2007: General Vision designs and releases the CM1K chip, successor of the ZISC, featuring 1024 neurons. Read more>>
  • Prestigious universities and laboratories are designing neuromorphic chips such as the MIT, Stanford, GorgiaTech, and more, but again when will they be available to the public? how easy to use?
  • 2011: General Vision starts marketing and licensing the technology under the NeuroMem tradename (i.e. Neuromorphic Memories)
  • What about FPGA? The NeuroMem IP is also available for FPGA and especially suitable for SOC running at high frequency. However, it is a viable solution only up to a certain number of neurons, after which the size and cost of the FPGA become unpractical for consumer appliances and IoT.